A 51K-gate low power ECL gate array family with metal-compiled and embedded SRAM

Author

Gray, D. ; Beeson, D. ; Davis, G. ; Hutchings, D. ; Thai, P. ; Wong, T.S. ; Kuroda, T. ; Nakamura, M. ; Noda, M.

Author_Institution

Synergy Semiconductor, Santa Clara, CA, USA

fYear

1993

fDate

9-12 May 1993

Abstract

A family of 80 ps, 1 mW/gate series-gated ECL (emitter coupled logic) gate arrays of up to 51K-gate density is described. The family supports both metal-compiled SRAM (static random-access memory) with a typical TAA of 2.5 ns and embedded SRAM with a TAA of 2.0 ns. Raw core densities of 1125 gates/mm² are achieved using a true ocean-of-cells, channel-less architecture. The arrays are fabricated using the ASSET-1 (all spacer-separated element transistor) 2-poly, 3-layer metal process with a conservative 1.2 μm emitter lithography

Keywords

emitter-coupled logic; 1.1 mW; 1.2 micron; 2 ns; 2-poly; 2.5 ns; 225 ps; 3-layer metal process; 80 ps; ASIC; ASSET-1; ECL gate array family; RAM intensive system element; all spacer-separated element transistor; bipolar; cell architecture; embedded SRAM; high-density; low power; macrocells; metal-compiled SRAM; semi-custom; series-gated; true ocean-of-cells; universal system element; CMOS technology; Clocks; Data processing; Delay; Frequency; Logic gates; Random access memory; Read-write memory; System performance; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590757

Filename

590757