An integrated floating point vector processor for DSP and scientific computing

Author

Spaderna, D. ; Green, P. ; Tam, K. ; Datta, T. ; Kumar, M.

Author_Institution

Sharp Microelectron. Technol. Inc., Vancouver, WA, USA

fYear

1989

fDate

2-4 Oct 1989

Firstpage

8

Lastpage

13

Abstract

The architecture of a high-performance floating-point microprocessor intended for computation-intensive applications is presented. Utilizing a massively parallel execution unit, very high bandwidth onchip memory, and extensive parallel address calculation hardware, the processor is expected to achieve peak execution rates of 400 MFLOPS for single-precision floating-point numbers. This type of performance is competitive with that of popular mainframe vector processors

Keywords

digital signal processing chips; parallel architectures; 400 MFLOPS; DSP; computation-intensive applications; floating-point microprocessor; integrated floating point vector processor; mainframe vector processors; massively parallel execution unit; onchip memory; parallel address calculation hardware; peak execution rates; scientific computing; single-precision floating-point numbers; Arithmetic; Bandwidth; Clocks; Digital signal processing; Hardware; Integrated circuit technology; Microelectronics; Read-write memory; Scientific computing; Vector processors;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-1971-6

Type

conf

DOI

10.1109/ICCD.1989.63318

Filename

63318