Title :
A single-chip stereo audio codec
Author :
Hamashita, Koichi ; Swanson, Eric
Author_Institution :
Asahi Kasei Microsystems Co., Kanagawa, Japan
Abstract :
Attention is given to a 16 b stereo audio codec that integrates two delta-sigma ADCs (analog-to-digital converters), two delta-sigma DACs (digital-to-analog converters), DAC analog postfilters, a voltage reference, and 64X digital interpolation and decimation filters. The delta-sigma modulators use single-loop fourth-order topology at a 64X oversampling rate. The DAC analog postfilters reduce sharp-rising quantization noise and improve timing jitter sensitivity. ADC and DAC dynamic ranges (0-22 kHz) are 88 dB and 87 dB, respectively. The 24.8 mm 2 chip is implemented in a 1.6 μm double-poly, double-metal CMOS process
Keywords :
audio coding; 0 to 22 kHz; 1.6 micron; 16 bit; DAC analog postfilters; decimation filters; delta-sigma ADCs; delta-sigma DACs; digital interpolation filters; double-metal CMOS process; double-poly; dynamic ranges; quantization noise; single-chip stereo audio codec; single-loop fourth-order topology; timing jitter sensitivity; voltage reference; Analog-digital conversion; Codecs; Delta modulation; Digital filters; Digital-analog conversion; Interpolation; Noise reduction; Quantization; Topology; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590813
