FSM-based programmable memory BIST with macro command

We propose a structured design methodology to construct FSM-based programmable memory BIST. The proposed BIST can be programmed on-line, with a "macro command", to select a test algorithm from a predetermined set of algorithms that are built in the memory BIST. In general, there are a variety of heterogeneous memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the BIST. We also develop a programmable memory BIST generator that automatically produces RTL model of the proposed BIST architecture for a given set of test algorithms. Experimental results show that the proposed method achieves a good flexibility with smaller circuit size compared with previous methods.