Title :
Statistical post-processing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies
Author :
Madge, Robert ; Rehani, Manu ; Cota, Kevin ; Daasch, W. Robert
Author_Institution :
LSI Logic Corp., Gresham, OR, USA
Abstract :
In sub-micron CMOS processes, it has become increasingly difficult to identify and separate outliers from the intrinsic distribution at test. This is due to the increasing inadequacy of reliability screens such as burn-in and IDDQ testing. Statistical Post-Processing (SPP) methods have been developed to run off-tester using the raw data generated from Automatic Test Equipment (ATE) and wafersort maps. Post-Processing modules include advanced IDDQ tests such as Delta IDDQ and the Nearest Neighbor Residual (NNR), as well as other non-IDDQ based reliability-focused modules. This work presents the application and results of SPP at LSI Logic on 0.18 μm CMOS products. Challenges of production implementation have been overcome, which include "user definable" adaptive threshold limits, handling multiple data sources, and data flow management. Burn-in data and customer Defects per Million units (DPM) data show a 30-60% decrease in failure rate with SPP implementation with very acceptable yield loss.
Keywords :
CMOS integrated circuits; automatic test equipment; failure analysis; integrated circuit reliability; integrated circuit testing; integrated circuit yield; production testing; statistical analysis; 0.18 μm CMOS products; 0.18 micron; ATE; IDDQ tests; LSI Logic; burn-in data; customer defects per million units data; data flow management; delta IDDQ; failure rate; intrinsic distribution; multiple data sources; nearest neighbor residual; outlier identification; reliability-focused modules; statistical post-processing; sub-micron CMOS processes; user definable adaptive threshold limits; variable thresholds; wafersort maps; yield loss; Automatic test equipment; CMOS logic circuits; CMOS process; CMOS technology; Distributed computing; Large scale integration; Logic testing; Manufacturing; Production; Reliability engineering;
Conference_Titel :
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN :
0-7695-1570-3
DOI :
10.1109/VTS.2002.1011113
