• DocumentCode
    18218
  • Title

    Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers

  • Author

    Kosuge, Atsutake ; Ishizuka, Shu ; Taguchi, Masao ; Ishikuro, Hiroki ; Kuroda, Tadahiro

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan
  • Volume
    62
  • Issue
    8
  • fYear
    2015
  • fDate
    Aug. 2015
  • Firstpage
    2122
  • Lastpage
    2131
  • Abstract
    An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.
  • Keywords
    CMOS integrated circuits; power consumption; telecommunication transmission lines; transceivers; CMOS process; FR4 test boards; bit rate 8.5 Gbit/s; energy-equipartitioned technique; full-3D EM-simulator; hysteresis characteristics; low-frequency components; multidrop bus interfaces; noncontact multidrop bus; power 75.6 mW; power consumption; receiver input point; signal branching point; size 90 nm; transceiver; transmission line couplers; voltage 1.2 V; Bandwidth; Couplers; Couplings; Gain; Impedance; Mathematical model; Power transmission lines; DRAM interface; multi-drop bus; transceiver; transmission line coupler;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2015.2437515
  • Filename
    7161411