Title :
Effect of on-chip ESD protection on 10 Gb/s receivers
Author :
Faust, Adam C. ; Srivastava, Ankit ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
Parasitic elements at the input of a high-speed receiver may limit bandwidth. A test chip was designed to quantify the impact of ESD protection on the performance of a 10 Gb/s receiver. Negative capacitance circuits are shown to improve signal integrity and their impact on ESD resiliency is measured.
Keywords :
electrostatic discharge; integrated circuit design; receivers; telecommunication equipment; ESD resiliency; bit rate 10 Gbit/s; high speed receiver; negative capacitance circuits; on chip ESD protection; parasitic elements; signal integrity; test chip; Bandwidth; Capacitance; Electrostatic discharge; Integrated circuit modeling; Power transmission lines; Receivers; Transmission line measurements;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
Conference_Location :
Anaheim, CA
Electronic_ISBN :
Pending
