DocumentCode
1825857
Title
Development of a fault model and test algorithms for embedded DRAMs
Author
Sachdev, Manoj ; Verstraelen, Math
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1993
fDate
17-21 Oct 1993
Firstpage
815
Lastpage
824
Abstract
Embedded DRAMs are an integral part of modern ICs. Owing to limited accessibility, the testing of embedded memories is a time consuming exercise. Such memories designed in a standard VLSI process show susceptibility to catastrophic as well as non-catastrophic defects. Taking into account catastrophic and non-catastrophic defects, an accurate and efficient fault model has been developed. Using this fault model linear test algorithms of complexity 8N and 9N have been developed
Keywords
CMOS integrated circuits; DRAM chips; VLSI; automatic testing; electrical engineering computing; failure analysis; fault diagnosis; fault location; integrated circuit modelling; integrated circuit testing; CMOSIC; ICs; catastrophic defects; embedded DRAMs; embedded memories; fault model; linear test algorithms; standard VLSI process; test algorithms; testing; Circuit faults; Circuit testing; Laboratories; Logic testing; Manufacturing; Modems; Random access memory; Read-write memory; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1993. Proceedings., International
Conference_Location
Baltimore, MD
Print_ISBN
0-7803-1430-1
Type
conf
DOI
10.1109/TEST.1993.470620
Filename
470620
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