Title :
A multiplier with redundant operands
Author :
Ferguson, M.I. ; Ercegovac, Milos D.
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
A drawback of using redundant number representation in arithmetic operations for general purpose processors is the need to convert the result to conventional notation before retiring the instruction. A possible solution is to allow forwarding of redundant-form results. To improve the efficiency of forwarding, functional units which can accept operands in redundant form are needed. To this end, a multiplier which accepts a redundant multiplicand and multiplier has been designed, simulated and compared with a conventional multiplier. The redundant multiplicand is converted to radix-2/sup k/ carry/save form before the multiples are formed. Simulations of a 32/spl times/32 bit multiplier show that for instructions which can use redundant form operands there is as much as 20% speedup compared to using conventional form.
Keywords :
CMOS logic circuits; VLSI; carry logic; circuit simulation; integrated circuit design; multiplying circuits; redundant number systems; 32 bit; CMOS; Cascade Automation; EPOCH; VLSI simulation program; arithmetic operations; carry/save arithmetic; forwarding efficiency; functional units; general purpose processors; multiplier; redundant multiplicand; redundant number representation; redundant operands; redundant-form results forwarding; speedup; Computer science; Delay; Digital arithmetic; Frequency; Pipelines; Process design; Very large scale integration;
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5700-0
DOI :
10.1109/ACSSC.1999.831921
