DocumentCode
18270
Title
Metal Floating Gate Memory Device With SiO2/HfO2 Dual-Layer as Engineered Tunneling Barrier
Author
Guoxing Chen ; Zongliang Huo ; Lei Jin ; Yulong Han ; Xinkai Li ; Su Liu ; Ming Liu
Author_Institution
Inst. of Microelectron., Beijing, China
Volume
35
Issue
7
fYear
2014
fDate
Jul-14
Firstpage
744
Lastpage
746
Abstract
Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2× nm. In this letter, it is demonstrated that stacked metal FG memory cell with SiO2/HfO2 dual-layer engineered tunneling barrier shows good memory characteristics. It presents favorable performance with lower operation voltage as well as enhanced program/erase speed. Furthermore, improvement of data retention is also obtained, proving that SiO2/HfO2 engineered tunnel barrier is promising for the improvement of metal FG memory performance.
Keywords
flash memories; hafnium compounds; high-k dielectric thin films; logic gates; silicon compounds; tunnelling; NAND flash technology node; SiO2-HfO2 engineered tunnel barrier; SiO2-HfO2; data retention; dual-layer engineered tunneling barrier; high-k dielectrics; metal floating gate memory deice; program-erase speed; stacked metal FG memory cell; Ash; Dielectrics; Hafnium compounds; Logic gates; Temperature; Tunneling; Metal floating gate memory; engineered tunneling barrier; engineered tunneling barrier.;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2014.2320971
Filename
6819826
Link To Document