Title :
3.3 GHz sense-amplifier in 0.18 μm CMOS technology
Author :
Wijetunga, P. ; Levi, A.F.J.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
The performance of a novel current-steering logic sense-amplifier (CSL-SA) is verified through measurements in 0.18 μm CMOS by implementing a CSL-SA flip-flop (CSL-SAFF). The measured operating frequency of 3.3 GHz in 0.18 μm is the highest performance results published to date in any CMOS technology. Measurements using 0.5, 0.35, 0.25 and 0.18 μm technologies show power and speed scaling of the new SA and SAFF to smaller geometries. The CSL-SA has better input sensitivity and 92% less clock-load compared to conventional voltage SAs.
Keywords :
CMOS logic circuits; flip-flops; high-speed integrated circuits; integrated circuit design; integrated circuit measurement; 0.18 to 0.5 micron; 3.3 GHz; CMOS current-steering logic sense-amplifier; CSL-SA flip-flop; clock-load; input sensitivity; operating frequency; power scaling; speed scaling; CMOS logic circuits; CMOS technology; Clocks; Current measurement; Flip-flops; Frequency measurement; Geometry; Power measurement; Velocity measurement; Voltage;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location :
Phoenix-Scottsdale, AZ
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1011465
