Bufferless Routing in Optical Gaussian Macrochip Interconnect

The ever increasing intra-chip and inter-chip traffic load in computing systems has been pushing traditional electronic interconnects to their limit in communication bandwidth, latency, and energy consumption. In order to achieve the high bandwidth and low latency required by intra-chip and inter-chip communications and mitigate the high interconnect power dissipation, optical interconnects have been considered as a promising candidate for intra-chip and inter-chip interconnections in next generation computing systems. In addition, packet switching is an efficient switching paradigm to fully utilize the communication bandwidth. However, due to lack of random access optical memory, it is challenging to implement all-optical packet switching in optical interconnects. In this paper, we exploit bufferless routing, a special type of packet-switching, to overcome the problem of lack of random access optical buffer. More specifically, we study bufferless routing in a novel optical multichip system, called Gaussian macrochip, where embedded chips are interconnected by an optical Gaussian network. By taking advantage of the underlying Hamiltonian cycles in the Gaussian network, we design a bufferless routing algorithm for the Gaussian macrochip, which routes packets along the shortest path in the absence of deflection, and guarantees that deflected packets reach their destinations within N hops. Our extensive simulation results demonstrate that by adopting the proposed routing algorithm, Gaussian macrochip can support much higher inter-chip communication bandwidth, has much shorter average packet delay, and is more power efficient than the previously proposed architectures for optical multichip systems.