DocumentCode :
1827817
Title :
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools
Author :
Gupta, Puneet ; Kahng, A.B. ; Sylvester, Dennis ; Yang, J.
Author_Institution :
ECE Dept., Univ. of California, San Diego, CA, USA
fYear :
2003
fDate :
2-6 June 2003
Firstpage :
16
Lastpage :
21
Abstract :
A minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requirements for dimensional variation control, especially in critical dimension (CD) 3σ, has become more stringent. To meet these requirements, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift mask (PSM) technologies are applied. These approaches result in a substantial increase in mask costs and make the cost of ownership (COO) a key parameter in the comparison of lithography technologies. No concept of function is injected into the mask flow; that is, current OPC techniques are oblivious to the design intent, and the entire layout is corrected uniformly with the same effort. We propose a minimum cost of correction (MinCorr) methodology to determine the level of correction for each layout feature such that prescribed parametric yield is attained with minimum total RET cost. We highlight potential solutions to the MinCorr problem and give a simple mapping to traditional performance optimization. We conclude with experimental results showing that substantial RET costs may be saved while maintaining a given desired level of parametric yield.
Keywords :
integrated circuit layout; optimisation; phase shifting masks; photolithography; proximity effect (lithography); MinCorr; correction minimum cost; critical dimension; dimensional variation control; lithographic correction methodology; minimum total RET cost; off-the-shelf sizing tools; optical lithography; optical proximity correction; phase shift mask; resolution enhancement techniques; Application specific integrated circuits; CMOS process; CMOS technology; Control systems; Costs; Hardware; Lithography; Maintenance; Modems; Permission;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
Type :
conf
DOI :
10.1109/DAC.2003.1218771
Filename :
1218771
Link To Document :
بازگشت