Nonlinear thermal stress & strain analysis of through silicon vias with different structures and polymer filling

Due to the differences in the thermal expansion coefficients of copper and silicon, a large thermal stress develops at the interface between a Cu-filled via and both the insulation layer and the surrounding silicon when the structure is subjected to temperature loading. In this paper four TSV geometries are considered in an effort to investigate the role of via geometry on stress relief. Thermo-mechanical finite element method (FEM) simulation software is used to analyze the influence of TSV shape on the nonlinear thermal stresses and strains generated under temperature cycling. The height (H) and radius (D) of a via are varied in the simulations in order to evaluate the magnitude and distribution of the thermal stress. In addition, various insulation materials and thicknesses are also considered in order to evaluate their thermo-mechanical behaviors. Thermal stress decreases with increasing SiO2 insulator thickness up to the process maximum of 1 um. In the case of Parylene, when the insulator thickness is less than 5 um, the stress value decreases to minimum for a polymer thickness of 5 um, thereafter increases showing an optimal thickness for minimum thermal stress. Finally, the vias with polymer filling are simulated.