A 10-bit 8.3MS/s switched-current successive approximation ADC for column-parallel imagers

This paper describes a switched-current successive approximation ADC for high resolution current mode imagers. The ADC is suitable to be integrated at the column level and operate in parallel. Designed in a 0.25 mum CMOS process, its core occupies only 24 mum x 200 mum and consumes 930 muW. Having a low input impedance of 0.6 Omega, it can connect directly to the imaging array while providing a stable bias voltage on the input line. The ADC is built around a single current comparator and an 11-bit sub-binary current DAC. It has no sampling stages. The output is digitally calibrated in order to compensate for component mismatch. Simulation results on both static and dynamic performance are presented. With calibration, the ADC achieves an effective resolution of 10 bits at 8.3 MS/s.