DocumentCode :
1829735
Title :
CSP package and ball design for board level characteristic
Author :
Wang, Yu Po ; Lin, Vito ; Chen, Eason ; Lee, Daniel
Author_Institution :
Siliconware Precision Ind. Co. Ltd., Taichung, Taiwan
fYear :
2011
fDate :
7-9 Dec. 2011
Firstpage :
824
Lastpage :
828
Abstract :
With the quick development of electronic products, IC chip with more functionalities, higher performance, miniaturization, higher reliability and lower cost have been requested intensely, especially in portable device domain such as cell phone, camera, notebook. Based on that, the electrical product using CSP series such as WLCSP, TFBGA, QFN etc. need further evaluation to meet those requirements. Although CSP package is the target for those new requirements, second level reliability must be addressed to meet the requirement of protability device, such as thermal cycle test (TCT). There are a lot of package design works done to ensure the best performance of CSP package for second level reliability. This paper aims at package design and ball stress analyses for CSP package by using Finite Element Method (FEM) for parameter studies such as ball size, ball matrix, ball pitch, ball opening, ball layout, silicon chip thickness, compound thickness, compound material and pre-mold material. The finite element model is assumed CSP package mounted on PCB simulating thermal cycle test. Firstly, this study is to compare the ball stress among test vehicle structure of CSP package with other CSP structures with the same package size and die size. From the results, the test vehicle of CSP package would perform the worst ball stress than others. And in order to improve the TCT performance of the test vehicle of CSP package, the optimized structure is then designed with some key factors to reduce the ball stress. CSP package with larger ball opening and higher ball stand-off height could reduce the ball stress about 9-20%. Besides that, smaller ball pitch, thinner die thickness, thicker compound thickness, higher CTE material property of compound and per-mold material also could reduce the ball stress and improve the TCT performance of CSP package from simulation results. Finally, this optimized design is underwent experiment to verify FEM works and compared with other CSP structu- es. With thoroughly package design support, the CSP package is successfully developed to provide a better routability, multiple rows of I/O and good SMT workability as well as optimized board level reliability.
Keywords :
chip scale packaging; elemental semiconductors; finite element analysis; printed circuit testing; printed circuits; reliability; silicon; stress analysis; workability; CSP package; CSP structures; CTE material property; IC chip; PCB simulating thermal cycle test; Si; TCT performance; ball design; ball layout; ball matrix; ball opening; ball pitch; ball size; ball stress analyses; board level characteristics; board level reliability; compound material; compound thickness; die size; electronic products development; finite element method; package design; package size; portable device domain; portable device requirement; premold material; second level reliability; silicon chip thickness; test vehicle structure; thermal cycle test; Chip scale packaging; Compounds; Finite element methods; Layout; Materials; Stress; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th
Conference_Location :
Singapore
Print_ISBN :
978-1-4577-1983-7
Electronic_ISBN :
978-1-4577-1981-3
Type :
conf
DOI :
10.1109/EPTC.2011.6184527
Filename :
6184527
Link To Document :
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