A scaled LSE wirelength model for VLSI global placement

Author

Jianli Chen ; Wenxing Zhu

Author_Institution

Center for Discrete Math. & Theor. Comput. Sci., Fuzhou Univ., Fuzhou, China

fYear

2014

fDate

19-21 Aug. 2014

Firstpage

881

Lastpage

885

Abstract

By ignoring some cell overlaps, the common objective of the very large scale integration (VLSI) global placement problem is to minimize its total half-perimeter wirelength (HP-WL). As the HPWL is not differentiable, the log-sum-exponential (LSE) wirelength model, one of the most powerful differentiable wirelength approximation functions, has been adopted in several nonlinear programming-based placers. In this paper, a scaled LSE (sLSE) wirelength model is proposed to approximate HPWL. In the sLSE wirelength model, the wirelength is calculated according to the exact wirelength of each net, which is a more exact approximation of HPWL. Based on the sLSE wirelength model and the framework of placer NTUplace3, an sLSE based nonlinear solver is generated to solve the VLSI global placement problem. Comparisons of experimental results show that the sLSE wirelength model can approximate HPWL more accurately than the LSE wirelength model.

Keywords

VLSI; integrated circuit interconnections; integrated circuit layout; nonlinear programming; HP-WL; LSE wirelength model; VLSI global placement; differentiable wirelength approximation; half-perimeter wirelength; log-sum-exponential wirelength model; nonlinear programming-based placers; nonlinear solver; very large scale integration global placement; Approximation methods; Benchmark testing; Computational modeling; Force; Runtime; Very large scale integration; Wires; HPWL; LSE wirelength model; VLSI Global placement; sLSE based nonlinear solver;

fLanguage

English

Publisher

ieee

Conference_Titel

Fuzzy Systems and Knowledge Discovery (FSKD), 2014 11th International Conference on

Conference_Location

Xiamen

Print_ISBN

978-1-4799-5147-5

Type

conf

DOI

10.1109/FSKD.2014.6980955

Filename

6980955