Title :
A portless SRAM Cell using stunted wordline drivers
Author :
Wieckowski, Michael ; Margala, Martin
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI
Abstract :
A minimum area portless SRAM cell is presented along with a stunted wordline driver. When compared to an iso-area 6T cell using logic design rules, the portless cell exhibits 22% higher static noise margin and 14% lower leakage with a 51% penalty in the on/off cell current ratio. Measurements from a fabricated test chip in 0.5 mum CMOS demonstrate functionality of the proposed cell and driver in an array, and for the first time, validate the portless concept in an isolated test cell.
Keywords :
CMOS logic circuits; SRAM chips; logic design; CMOS; logic design rules; portless SRAM cell; size 0.5 mum; stunted wordline drivers; Circuits; Feedforward systems; Logic design; Low voltage; Random access memory; Semiconductor device measurement; Signal to noise ratio; Stability; Testing; Voltage control;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541485
