An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

Author

Nishi, Yoshinori ; Abe, Koichi ; Ribo, Jerome ; Roederer, Benoit ; Gopalan, Anand ; Benmansour, Mohamed ; Ho, An ; Bhoi, Anusha ; Konishi, Masahiro ; Moriizumi, Ryuichi ; Pathak, Vijay ; Gondi, Srikanth

Author_Institution

R&D Div., Kawasaki Microelectron. America Inc., San Jose, CA

fYear

2008

fDate

3-5 Nov. 2008

Firstpage

37

Lastpage

40

Abstract

A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm². Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.

Keywords

CMOS integrated circuits; application specific integrated circuits; peripheral interfaces; transceivers; 4-channel transceiver; ASIC; CEI6G-LR standard; CEI6G-SR standard; CMOS process; PCIe standards; SAS-6G standard; XAUI standards; bit rate 1.25 Gbit/s to 6.25 Gbit/s; power dissipation; size 90 nm; small area PHY transceiver; voltage 1 V; Application specific integrated circuits; Circuit testing; Clocks; Driver circuits; Phase locked loops; Photonic band gap; Routing; Solid state circuits; Throughput; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Conference_Location

Fukuoka

Print_ISBN

978-1-4244-2604-1

Electronic_ISBN

978-1-4244-2605-8

Type

conf

DOI

10.1109/ASSCC.2008.4708723

Filename

4708723