A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS

Author

Shiyu Su ; Tu-I Tsai ; Sharma, Parmanand ; Chen, Mike Shuo-Wei

Author_Institution

Univ. of Southern California, Los Angeles, CA, USA

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A 12-bit Hybrid DAC architecture with split Nyquist (1 GS/s) and delta-sigma modulator path (8 GS/s) has been proposed and implemented in 65 nm CMOS. Based on the hybrid architecture, the delta-sigma assisted pre-distortion scheme compensates for the current steering cell mismatch that further reduces the analog circuit complexity and area. The proposed 8X unrolled pipeline delta-sigma modulator allows for high-speed third-order noise shaping with digital standard cell design flow. The measured SFDR achieves record 91-75 dB over 500 MHz Nyquist band.

Keywords

CMOS integrated circuits; delta-sigma modulation; integrated circuit design; integrated circuit noise; CMOS technology; SFDR; analog circuit complexity; current steering cell mismatch; delta-sigma assisted predistortion scheme; digital standard cell design flow; high-speed third-order noise shaping; hybrid DAC architecture; noise figure 91 dB to 75 dB; size 65 nm; split Nyquist band architecture; unrolled pipeline delta-sigma modulator; word length 12 bit; CMOS integrated circuits; Clocks; Computer architecture; Frequency measurement; Linearity; Microprocessors; Modulation; calibration; current steering DAC; hybrid;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858434

Filename

6858434