A 960MS/s DAC with 80dB SFDR in 20nm CMOS for multi-mode baseband wireless transmitter

Author

Wei-Hsin Tseng ; Pao-Cheng Chiu

Author_Institution

MediaTek, Hsinchu, Taiwan

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A 960MS/s calibrated digital-to-analog converter (DAC) and low pass reconstruction filter are fabricated in 20nm CMOS. The calibration is implemented without an extra analog-to-digital converter (ADC) by reconfiguring the filter as the integrator for an incremental ADC which is used to digitize DAC cell mismatch. The digital input to the DAC is compensated by a look-up table to correct DAC mismatch in real-time. Before calibration, DNL is -1.1/+0.7LSB and INL is -2.1/+0.3LSB. After calibration DNL and INL are improved to -0.2/+0.2LSB and -0.3/+0.2LSB respectively. This 10b DAC achieves 80.2dB SFDR after calibration, and occupies 0.01mm² for an I/Q DAC pair which is 12.5% of the area for an uncalibrated I/Q DAC pair.

Keywords

CMOS digital integrated circuits; calibration; digital-analogue conversion; low-pass filters; radio transmitters; table lookup; SFDR; calibrated digital-to-analog converter; digitize DAC cell mismatch; incremental ADC; look-up table; low pass reconstruction filter; multimode baseband wireless transmitter; size 20 nm; uncalibrated I/Q DAC pair; word length 10 bit; Calibration; Converters; Digital-analog conversion; Digitization; Low pass filters; 20nm CMOS; DAC; calibration; incremental ADC and current mismatch temperature drift; reconstruction filter;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858435

Filename

6858435