An effective design technique to reduce leakage power

Now a day´s low power Design is a essential requirement for This electronic document is a “live” template. The various components of your paper [title, text, heads, etc.] are already defined on the style hardware implementation. Technology moving into deep submicron region causes increase in leakage power. MTCMOS is promising technique for reducing leakage power but use of this technique results in delay overhead in active mode and data retention problem for sequential circuit. This paper propose a design technique for reducing the leakage power and data loss problem during sleep mode. Simulation results show that reduction in leakage power while preserving the state of the circuit.