• DocumentCode
    183196
  • Title

    A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist

  • Author

    Olieman, Erik ; Annema, Anne-Johan ; Nauta, Bram

  • Author_Institution
    Univ. of Twente, Enschede, Netherlands
  • fYear
    2014
  • fDate
    10-13 June 2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than -50dBc IM3 over Nyquist at a sampling rate of 11GS/s, occupying only 0.04mm2 and consuming 110mW from a single 1V supply.
  • Keywords
    digital-analogue conversion; multiplexing equipment; silicon-on-insulator; 9-bit interleaved DAC; FDSOI; SFDR across Nyquist; Si; back gates; bias voltage; clock timing; current-steering digital-to-analog converter; main error mechanisms; multiplexer transistors; power 110 mW; size 28 nm; voltage 1 V; word length 9 bit; CMOS integrated circuits; Clocks; Multiplexing; Switches; Timing; Transistors; Very large scale integration; DAC; FDSOI; interleaving; quad-switching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits Digest of Technical Papers, 2014 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4799-3327-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2014.6858437
  • Filename
    6858437
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=183196