ROM based logic (RBL) design: High-performance and low-power adders

Author

Paul, Bipul C. ; Fujita, Shinobu ; Okajima, Masaki

Author_Institution

Toshiba America Res. Inc., San Jose, CA

fYear

2008

fDate

18-21 May 2008

Firstpage

796

Lastpage

799

Abstract

We present a ROM based logic design technique using reduced ROM size by eliminating identical rows and columns along with fast and low power single transistor cells. It substantially reduces the critical path length and thereby, improves the performance yet achieves low-power dissipation due to reduced number of switching. We present the ROM based design of a carry select adder (CSA) and two parallel prefix adders, which achieve more than 30% (in 32 bit adder) delay reduction over their conventional designs at 90 nm technology with as low as 9% (CSA) active power increase.

Keywords

adders; network synthesis; power transistors; read-only storage; switching circuits; ROM based logic design technique; carry select adder; high performance adders; low power adders; low power dissipation; low power single transistor cells; parallel prefix adders; read only memory; size 90 nm; Added delay; Adders; CMOS technology; Decoding; Energy consumption; High performance computing; Logic circuits; Logic design; Logic functions; Read only memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4244-1683-7

Electronic_ISBN

978-1-4244-1684-4

Type

conf

DOI

10.1109/ISCAS.2008.4541538

Filename

4541538