Analysis of CMOS interconnections combining LE-FDTD method and SOC procedure

Author

Alimenti, F. ; Palazzari, V. ; Placidi, P. ; Stopponi, G. ; Scorzoni, A. ; Roselli, L.

Author_Institution

DIEI, Perugia Univ., Italy

Volume

2

fYear

2002

fDate

2-7 June 2002

Firstpage

879

Abstract

This work describes the application of the Lumped Element-Finite Difference Time Domain (LE-FDTD) method to the rigorous analysis of CMOS interconnections. In particular the frequency-dependent line parameters are evaluated in a wide (DC to 100 GHz) bandwidth. To obtain very accurate results the Short-Open Calibration (SOC) procedure has been adopted. With such an approach, simple lumped generators and loads can be used to excite and terminate the structure under analysis, in substitution of more complex boundary conditions. The technique has been validated against experimental results from the literature showing a good agreement.

Keywords

CMOS integrated circuits; calibration; finite difference time-domain analysis; integrated circuit interconnections; integrated circuit modelling; 0 to 100 GHz; CMOS interconnections; LE-FDTD method; SOC procedure; complex boundary conditions; frequency-dependent line parameters; lumped element-finite difference time domain method; lumped generators; short-open calibration procedure; Boundary conditions; CMOS technology; Calibration; Computational modeling; Finite difference methods; Frequency; Impedance; Integrated circuit interconnections; Time domain analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2002 IEEE MTT-S International

Conference_Location

Seattle, WA, USA

ISSN

0149-645X

Print_ISBN

0-7803-7239-5

Type

conf

DOI

10.1109/MWSYM.2002.1011770

Filename

1011770