A multilevel inverter with reduced number of switches

A multilevel inverter is a power electronic device that is used for high voltage and high power applications, with the added advantages of low switching stress and lower total harmonic distortion (THD), hence reducing the size and bulk of the passive filters. This paper proposes a new topology of a cascaded multilevel inverter that utilizes less number of switches than the conventional topology. Therefore with less number of switches in the circuit, there will be a reduction in the gate driver circuits and also in effect fewer switches will be conducting for specific intervals of time. The circuitry consists of smaller multilevel inverter blocks connected in series to achieve its characteristic output waveform. A seven level inverter will be simulated with the implementation of PWM techniques and its effect on the harmonic spectrum will be analyzed. The system will be modelled with the help of MATLAB/SIMULINK.