Title :
Extreme thin integrated circuits
Author :
Haberger, K. ; Bollmann, D. ; Landesberger, C. ; Ramm, P. ; Seitz, S. ; Hieber, K.
Author_Institution :
Fraunhofer Inst. for Solid State Technol., Munchen, Germany
Abstract :
The fabrication technology and electrical behavior of extremely thin integrated circuits are investigated and discussed. Wafers with implemented test chips are stuck to a handling substrate with an organic glue and then thinned by different methods. The mechanical properties of these extremely thin silicon chips have been studied and preliminary electrical results of chip foils laminated to another substrate are reported
Keywords :
CMOS integrated circuits; integrated circuit technology; silicon-on-insulator; BESOI; CMOS line; chip foils; electrical behavior; extremely thin Si chips; extremely thin integrated circuits; fabrication technology; handling substrate; mechanical properties; organic glue; reversible SOI process; thinning; Chemical lasers; Chemical processes; Circuit testing; Mechanical factors; Ring lasers; Silicon; Thermal expansion; Thermal force; Wafer bonding; Wet etching;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.503341
