Title :
An enhanced floating point coprocessor for embedded signal processing and graphics applications
Author_Institution :
ARM Inc., USA
Abstract :
There has been a marked interest in enhancing general purpose microprocessors to accommodate signal processing, primarily to improve audio and video compression routines and speech recognition algorithms. Presented here are several enhancements incorporated in the ARM VFPv1 floating point architecture which have demonstrated significant performance improvements on critical signal processing kernels. The first implementation of the VFPv1 architecture is the VFP10 floating point coprocessor macrocell. Discussed are the FMAC (floating point multiply-accumulate chained) instructions, a separate load/store pipeline for parallel processing of arithmetic and transfer operations, and SIMD capabilities for most arithmetic instructions designed to take advantage of a new recirculating register file structure.
Keywords :
FIR filters; computer graphics; coprocessors; digital signal processing chips; floating point arithmetic; parallel architectures; ARM VFPv1 floating point architecture; FMAC; SIMD capabilities; VFP10 floating point coprocessor macrocell; arithmetic instructions; audio compression; embedded signal processing; enhanced floating point coprocessor; floating point multiply-accumulate chained instructions; general purpose microprocessors; graphics applications; load/store pipeline; parallel processing; performance; recirculating register file structure; signal processing kernels; speech recognition; video compression; Coprocessors; Floating-point arithmetic; Kernel; Macrocell networks; Microprocessors; Pipelines; Signal processing algorithms; Speech recognition; Video compression; Video signal processing;
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5700-0
DOI :
10.1109/ACSSC.1999.832312