• DocumentCode
    1835899
  • Title

    LTSs for translation validation of (multi-clocked) SIGNAL specifications

  • Author

    Peralta, Julio C. ; Gautier, Thierry ; Besnard, Loic ; Le Guernic, Paul

  • Author_Institution
    Centre Rennes-Bretagne Atlantique, INRIA, Rennes, France
  • fYear
    2010
  • fDate
    26-28 July 2010
  • Firstpage
    199
  • Lastpage
    208
  • Abstract
    Design of critical embedded systems demands for guarantees on the reliability of the implementation/compilation of a specification. In general, this guarantee takes either the form of a certified compiler, or the validation of each translation. Here we adopt the translation validation approach. In particular, we translate both the SIGNAL specification and the associated C simulator into LTSs. Then, an appropriate (successful) preorder test between both LTSs can be interpreted as a refinement between the C implementation and its source SIGNAL specification, otherwise, counter-examples are generated automatically. The feasibility of our approach is shown through examples.
  • Keywords
    embedded systems; program compilers; program verification; software reliability; C simulator; LTS; certified compiler; critical embedded systems; multiclocked signal specifications; preorder test; translation validation; Clocks; Delay; Equations; Kernel; Mathematical model; Semantics; Synchronization; Concurrent Programs; Labelled Transition Systems; Multi-clocked Synchronous Programs; Refinement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods and Models for Codesign (MEMOCODE), 2010 8th IEEE/ACM International Conference on
  • Conference_Location
    Grenoble
  • Print_ISBN
    978-1-4244-7885-9
  • Electronic_ISBN
    978-1-4244-7886-6
  • Type

    conf

  • DOI
    10.1109/MEMCOD.2010.5558632
  • Filename
    5558632