Broadband passive RLGC(f) modeling for on-chip interconnect design

To design state-of-the-art on-chip interconnect structures, efficient modeling tools are needed that accurately incorporate all substrate loss mechanisms and the finite conductivity and shape of the metallic interconnects. In this contribution, accurate broadband macromodels are conceived for the per unit length resistance (R), inductance (L), conductance (G) and capacitance (C) parameters of such on-chip interconnects. By means of adaptive frequency sampling (AFS) the simulation cost to obtain these models is small. Additionally, passivity can be assessed and enforced. The technique is applied to the analysis of an inverted embedded microstrip (IEM) line. Compared to commercial simulation software, both in frequency and time domain, excellent agreement and superior efficiency is observed, illustrating the method´s applicability for on-chip design purposes.