Scalable event routing in hierarchical neural array architecture with global synaptic connectivity

An asynchronous communication scheme for scalable routing of spike events in large-scale neuromorphic hardware is presented. The routing scheme extends the Address-Event Representation (AER) protocol for spike event communication to a modular, hierarchical architecture supporting efficient implementation of global synaptic inter-connectivity across a cellular matrix of message parsing axonal relay nodes at varying spatial scales. This paper presents a probabilistic framework for analyzing trade-offs in throughput and latency of synaptic communication as a function of load and geometry, and simulation results verifying the statistics of traffic flow across the architecture.