Title :
Scaling challenges for 0.13 μm generation shallow trench isolation
Author :
Kuhn, Kelin J. ; Mei, Din-how ; Post, Ian ; Neirynck, Jan
Author_Institution :
Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
Scaling shallow trench isolation (STI) from the 0.18 μm to 0.13 μm generation has offered many new challenges for semiconductor manufacturing. Two are discussed in this paper. The first is delivering a capable gapfill process for high aspect ratio trenches while maintaining isolation punchthrough margin (as well as low junction capacitance). The second is trading off NMOS mobility degradation generated by the use of compressive HDP films against the improved gapfill, wet-etch, and polish properties of these films
Keywords :
MOS integrated circuits; capacitance; carrier mobility; etching; integrated circuit yield; isolation technology; plasma deposition; polishing; 0.13 micron; NMOS mobility degradation; aspect ratio trenches; compressive HDP films; gapfill process; isolation punchthrough margin; junction capacitance; polish properties; scaling; semiconductor manufacturing; shallow trench isolation; wet-etch; Compressive stress; Degradation; Displays; Isolation technology; MOS devices; Packaging; Plasma density; Stress measurement; Temperature; Thermal stresses;
Conference_Titel :
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-6731-6
DOI :
10.1109/ISSM.2001.962945
