Title :
NPU ASIC chip tester
Author :
Ren, Gonghai ; Wang, Ling ; Gao, Deyuan
Author_Institution :
Inst. of ASIC, Northwestern Polytech. Univ., Xian, China
Abstract :
NPU ASIC chip tester is a low cost, functional tester. It can test chips in three modes: off-line, on-line, interactive. It can test chips that have up to 128 pins. Each test driver of this tester is programmable independently. Its hardware is implemented mainly using Xilinx FPGAs. It has a powerful software package, which facilitates the design of test programs and the analysis of test results. This software package also provides interfaces with many current EDA tools
Keywords :
application specific integrated circuits; integrated circuit testing; EDA tools; NPU ASIC chip tester; Xilinx FPGAs; functional testing; interactive testing; interface; off-line testing; on-line testing; programmable drivers; software package; Application specific integrated circuits; Buffer storage; Computer architecture; Cost function; Delay; Pins; Software packages; Software testing; System testing; Timing;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.503549
