DC bias effects on bulk silicon and porous silicon substrates

Author

Itotia, I.K. ; Drayton, R.F.

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., USA

Volume

2

fYear

2003

fDate

22-27 June 2003

Firstpage

663

Abstract

The relationship between attenuation and biasing for CPW architectures on bulk and porous silicon films is investigated. Biasing effects on low resistivity silicon can have loss variations as high as 34 dB/cm under negative bias (0 to -10 V) and 2 dB/cm for positive bias (0 to 10 V) conditions. While the inclusion of an oxide film substantially reduces loss variation (< 0.1 dB/cm), the use of a 68% porous silicon film can provide further stability (< 0.01 dB/cm) in addition to lowered attenuation in the range of 1.3 to 3 dB/cm from 5 to 20 GHz.

Keywords

S-parameters; coplanar waveguides; elemental semiconductors; permittivity; porous semiconductors; silicon; substrates; CPW attenuation; DC bias dependent attenuation; S-parameter response; Si; bulk silicon films; dielectric constant; low resistivity silicon; negative bias; porous silicon films; positive bias; printed interconnects; silicon substrates; Artificial intelligence; Buildings; Circuit synthesis; Conductivity; Coplanar waveguides; Costs; Personal digital assistants; Radio frequency; Silicon; Steel;

fLanguage

English

Publisher

ieee

Conference_Titel

Antennas and Propagation Society International Symposium, 2003. IEEE

Conference_Location

Columbus, OH, USA

Print_ISBN

0-7803-7846-6

Type

conf

DOI

10.1109/APS.2003.1219323

Filename

1219323