Title :
Copper-filled through wafer vias with very low inductance
Author :
Jenkins, Keith A. ; Patel, Chirag S.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
The inductance of through-wafer vias in a new via technology in silicon is reported. The technology uses copper filled vias with 70 μm diameters. Measurements by network analyzer up to 40 GHz show that the vias have an inductance of approximately 0.15 pH/μm, the smallest reported value for vias in silicon.
Keywords :
copper; inductance; integrated circuit interconnections; integrated circuit metallisation; 40 GHz; 70 micron; Cu; low inductance vias; metal filled vias; network analyzer measurements; through wafer vias; Copper; Frequency; Impedance measurement; Inductance measurement; Integrated circuit interconnections; Power system interconnection; Probes; Silicon; Thickness measurement; Wiring;
Conference_Titel :
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International
Print_ISBN :
0-7803-8752-X
DOI :
10.1109/IITC.2005.1499957
