Title :
The next-generation SPARC multiprocessing system architecture
Author :
Frailong, J.-M. ; Cekleov, M. ; Sindhu, P. ; Gastinel, J. ; Splain, M. ; Price, J. ; Singhal, A.
Author_Institution :
Xerox Palo Alto Res. Center, CA, USA
Abstract :
The SPARCcenter 2000´s multiprocessor architecture defines a set of functional building blocks that share a common hardware interface, the XDBus. This modular approach permits the implementation of multiprocessors covering a wide range of performance and cost. It allows the ratio of processing power, memory capacity, and I/O bandwidth to be varied within a given machine while permitting system designers to address different points on the overall performance spectrum. Each functional block (processor, memory, I/O) consists of a small number of highly integrated chips. The architecture provides a number of features to support high-performance symmetric multiprocessor software. These include hardware caches, TLB coherency, dynamic interrupt dispatching with source identification, weak write ordering, block copy hardware, and hardware performance monitoring.<>
Keywords :
multiprocessing systems; parallel architectures; system buses; workstations; I/O bandwidth; SPARC multiprocessing system architecture; SPARCcenter 2000; TLB coherency; XDBus; block copy hardware; dynamic interrupt dispatching; functional building blocks; hardware caches; hardware interface; hardware performance monitoring; integrated chips; memory capacity; modular approach; processing power; source identification; symmetric multiprocessor software; weak write ordering; Backplanes; Computer architecture; Computer interfaces; Delay; Hardware; Interleaved codes; Multiprocessing systems; Packaging; Scalability; Sun;
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
DOI :
10.1109/CMPCON.1993.289717
