Race-condition-aware retiming

Retiming transformation relocates registers in a circuit to shorten the clock cycle time. However, with the advent of deep sub-micron era, the hold constraints often limit the smallest feasible clock period that the retiming transformation can achieve. Therefore, a combination of retiming transformation and delay insertion may lead to further clock period reduction. In this paper, we propose a retiming methodology, called race-condition-aware, retiming (RCA retiming), to determine, a retiming solution by relaxing the critical hold constraints that actually limit the circuit performance. Our objective is not only to optimize the clock period, but also attempts to minimize the required inserted delay. Experimental data show that our approach can make significant improvement in the circuit performance with small overhead in the circuit area.