Challenge and innovation of VLSI design below 100nm

In the design of VLSIs, its goal is to implement higher integration and higher performance through the innovation of architecture, design tool and process technology. As the device minimum dimension becomes smaller below 100nm, diversified serious issues, including signal integrity and power dissipation, are being emerged. In order to overcome these barriers, the necessity of tight coupling, or effective joint activities which combine solutions of various layers between design and manufacturing fields will be discussed. Furthermore, possible countermeasures to overcome the technological barriers such as fluctuation in device characteristics estimated in the 45nm generation will be discussed.