Title :
2 k gate circuits with 125 ps gate delay using GaAs HFET technology
Author :
Leung, W.B. ; Lo, Y.K. ; Oh, Y.T. ; Oswald, W.A. ; Poon, E.K. ; Reid, C.E. ; Ackner, L.E. ; Poon, T.C.
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
Abstract :
Four digital circuits were processed with the self-aligned refractory gate process in the DARPA III GaAs pilot line. The GaAs-AlGaAs heterostructure E/D FET technology (HFET) with 1- mu m channel length and a nominal power supply of 2 V was used to implement a 32-bit ALU (arithmetic logic unit), a dual 8*8 parallel multiplier, a quad 4-bit adder, and a SRAM tester. The measured propagation delay per gate is 125 ps for the ALU and 132 ps for the multiplier.<>
Keywords :
III-V semiconductors; adders; aluminium compounds; digital arithmetic; digital integrated circuits; field effect integrated circuits; gallium arsenide; integrated circuit testing; integrated logic circuits; integrated memory circuits; multiplying circuits; random-access storage; 1 micron; 125 ps; 132 ps; 2 V; 32 bit; ALU; DARPA III; GALPAT test; GaAs pilot line; GaAs-AlGaAs; HFET; SRAM tester; arithmetic logic unit; digital circuits; gate delay; heterostructure E/D FET technology; logic circuits; memory circuits; parallel multiplier; propagation delay per gate; quad 4-bit adder; self-aligned refractory gate process; static RAM; Adders; Arithmetic; Delay; Digital circuits; FETs; Gallium arsenide; HEMTs; Logic testing; MODFETs; Power supplies;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/GAAS.1989.69293
