Simple self-aligned air-gap interconnect process with Cu/FSG structure

Author

Noguchi, Junji ; Fujiwara, Tsuyoshi ; Sato, Kiyohiko ; Nakamura, Takaharu ; Kubo, Maki ; Uno, Shouichi ; Ishikawa, Kensuke ; Saito, Tutsuyuki ; Konishi, Nobuhiro ; Yamada, Youhei ; Tamaru, Tsuyoshi

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2003

fDate

2-4 June 2003

Firstpage

68

Lastpage

70

Abstract

A novel self-aligned air-gap interconnect process with Cu/FSG structure was proposed. The key feature is the use of an easily removal sacrifice film by dry-etching process with a reducing gas. This process consists of a conventional Cu damascene process with 130 nm node CMOS technology. In this study, a 2 level Cu interconnect was fabricated and the effective dielectric constant of 2.3∼2.6 has been successfully achieved. These are consistent with the capacitance reduction by 37∼41% compared with a conventional Cu/FSG structure.

Keywords

CMOS integrated circuits; air gaps; capacitance; copper; glass; integrated circuit interconnections; permittivity; sputter etching; CMOS technology; Cu damascene process; Cu interconnect; Cu/FSG structure; Cu/fluorinated silicon glass structure; capacitance; dielectric constant; dry etching; self aligned air gap interconnect process; Air gaps; CMOS process; CMOS technology; Capacitance; Chemicals; Delamination; Delay; Dielectric constant; Large scale integration; Silicon carbide;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International

Print_ISBN

0-7803-7797-4

Type

conf

DOI

10.1109/IITC.2003.1219715

Filename

1219715