A systematic approach to interconnect modeling and process monitoring

Author

Nagaraj, N.S. ; Kulkarni, Mak ; Bonifield, Tom ; Narasimha, Usha ; Hossain, Lmran ; Zabierek, Corbett

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2003

fDate

2-4 June 2003

Firstpage

114

Lastpage

116

Abstract

This paper describes a systematic approach to the use of electrical measurements for interconnect modeling and process monitoring. A fast and area efficient technique to measure interconnect capacitance in a scribe line is discussed. The benefits of this technique in monitoring interconnect process, and in fanning out technology to multiple fabs, in monitoring wafer-to-wafer/lot-to-lot variations and in accurate modeling of capacitance are illustrated using the results from 130 nm copper technology.

Keywords

capacitance measurement; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; process monitoring; copper technology; electrical measurements; interconnect capacitance; interconnect modeling; interconnect process; multiple fabs; process monitoring; Area measurement; Capacitance measurement; Circuit testing; Current measurement; Electrical resistance measurement; Integrated circuit interconnections; Monitoring; Semiconductor device measurement; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International

Print_ISBN

0-7803-7797-4

Type

conf

DOI

10.1109/IITC.2003.1219728

Filename

1219728