Effective noise minimization in multichannel recording circuits processed in modern technologies for neurobiology experiments

This paper presents an effective method of input referred noise minimization (IRN) of recording stages dedicated to neurobiology experiments and processed in submicron or nanometer technologies. We analyze different approaches for IRN minimization and propose solution based on the on-chip analogue noise averaging. The proposed approach allows for almost 2.5 times IRN minimization with only 8 time power consumption increase whereas other on-chip analogue methods provides much less noise minimization efficiency. The method is confirmed by measurements of 8-channel integrated circuit fabricated in 180nm commercial process. The chip is composed of the 8-recording channels that are individually digitally assisted for enlarging IC functionality. The recording part is divided into two separate channels, i.e. an Action Potential (AP) stage and a Local Field Potential (LFP) stage. The voltage gain of the AP and LFP stages can be switched between 56/50 dB and 50/45 dB respectively. Corner frequencies of a particular stages can be digitally controlled in a wide range, i.e. the upper cut-off frequency can be changed in the 20 Hz - 2 kHz (LFP stage) while the lower cut-off frequency can be tuned at the 120 mHz - 3 kHz (LFP and AP stage). The upper cut-off frequency of the AP stage is equal to 6.9 kHz. A single recording channel is supplied from ±0.9 V and consumes about 4.8 μW of power. For a default channel configuration the Input Referred Noise is equal to 5.6 μV resulting in 4.38 of Noise Efficiency Factor (NEF) while for on-chip averaging mode enabled the IRN can be limited to 2.4 μV resulting in 5.3 of NEF.