DocumentCode :
1847288
Title :
Prediction of thermal performance of flip chip-plastic ball grid array (FC-PBGA) packages: effect of substrate physical design
Author :
Ramakrishna, K. ; Lee, T-Y Tom
Author_Institution :
Adv. Process Dev. & External Res., Motorola Inc., Austin, TX, USA
fYear :
2002
fDate :
2002
Firstpage :
528
Lastpage :
537
Abstract :
Package substrate physical design effects thermal conduction in the substrate and, hence, the thermal performance of the package. Package physical design involves geometric, material, and feature layout parameters. Effect of these physical design parameters on the thermal performance (characterized by junction to ambient thermal resistance, Θja, junction-to-board thermal resistance Ψjb, and junction to case thermal resistance ΨjT) of flip-chip plastic ball grid array (FC-PBGA) has been studied using experimentally validated conjugate heat transfer models. Package level thermal performance of flip-chip plastic ball grid array (FC-PBGA) packages has been predicted using experimentally validated mechanistic methodologies. The resulting conjugate heat transfer models have been solved using methods of computational fluid dynamics (CFD) under natural and forced convection for freestream velocities upto 2 m/s. The following ranges of parameters have been investigated: substrate size of 25 mm, die sizes of 6.19×7.81 mm and 9.13×12.95 mm, substrate (via density) thermal conductivities: no vias to 5 W/(m K), C4 pitch: 250 μm, natural and forced convection flows, the later with freestream velocities 0.5 to 2 m/s. Based on this study the following conclusions have been drawn: 1. It is concluded that thermal vias (and hence the thermal conductivity of the substrate under the die) have significantly higher impact on package thermal performance than the substrate vias outside the die foot print. 2. By strategically placing sufficiently number of vias in the substrate, the thermal resistance of the package can be decreased by 35-40% thereby pushing the limits of power dissipation under constrained conditions. 3. It is noted that increasing the number of visa under the die that results in thermal conductivity above 2 W/(m K), the thermal performance of the packages improve very little showing diminishing returns.
Keywords :
ball grid arrays; computational fluid dynamics; flip-chip devices; forced convection; natural convection; plastic packaging; substrates; thermal conductivity; thermal resistance; computational fluid dynamics; conjugate heat transfer model; flip-chip plastic ball grid array package; forced convection; natural convection; power dissipation; substrate physical design; thermal characteristics; thermal conductivity; thermal resistance; thermal via; Computational fluid dynamics; Conducting materials; Electronics packaging; Foot; Heat transfer; Plastic packaging; Resistance heating; Thermal conductivity; Thermal force; Thermal resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Thermal and Thermomechanical Phenomena in Electronic Systems, 2002. ITHERM 2002. The Eighth Intersociety Conference on
ISSN :
1089-9870
Print_ISBN :
0-7803-7152-6
Type :
conf
DOI :
10.1109/ITHERM.2002.1012501
Filename :
1012501
Link To Document :
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