Title :
Implementation of AES S-Boxes using combinational logic
Author :
Rachh, Rashmi Ramesh ; Mohan, P. V Ananda
Author_Institution :
Dept. of Comput. Sci., KLE Coll. of Eng. & Technol., Belgaum
Abstract :
In this paper, two approaches for implementation of the 8-bit S-Box suitable for FPGA based solutions are considered. These use (a) synthesis of the logic functions using Boolean simplification of the truth table of all the columns and (b) synthesis of the ANF (Algebraic Normal form) logic functions using AND and EXOR gates. The hardware and computation time evaluation for both the options are also presented.
Keywords :
Boolean algebra; field programmable gate arrays; logic design; AES 8-bit S-boxes; ANF; Boolean simplification; FPGA; algebraic normal form; combinational logic; field programmable gate array; truth table; Costs; Cryptography; Delay; Field programmable gate arrays; Hardware; Iterative algorithms; Logic functions; NIST; Read only memory; Table lookup;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4542162
