A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder

Author

Lee, Jun-Young ; Lee, Jae-Jin ; Jeong, MooKyoung ; Eum, Nakwoong ; Park, SeongMo

Author_Institution

Electron. & Telecommun. Res. Inst., Daejeon

fYear

2008

fDate

18-21 May 2008

Firstpage

3462

Lastpage

3465

Abstract

In this paper, we implement the configurable processor for CAVLC function module of a H.264/AVC baseline profile decoder as the starting point to implement the H.264/AVC decoder system in a multiprocessor platform. The requirements of the implementations are the low-power processor and speed optimized algorithms tailored to the processor architecture. An arithmetic formula mapping method for fast CAVLC algorithms and a dual-issue VLIW processor architecture with custom instructions are proposed. The experiment results show that the synthesized processor has about 75 K gates and can carry out the decoding of 30-fps CIF (352x288 pixels) images around 120 Mega cycles.

Keywords

application specific integrated circuits; decoding; video coding; ASIP; CAVLC; H.264/AVC decoder; application specific instruction processor; baseline profile decoder; low-power processor; multiprocessor platform; speed optimized algorithms; Algorithm design and analysis; Application software; Application specific processors; Arithmetic; Automatic voltage control; Computer architecture; Decoding; Signal processing algorithms; Software algorithms; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4244-1683-7

Electronic_ISBN

978-1-4244-1684-4

Type

conf

DOI

10.1109/ISCAS.2008.4542204

Filename

4542204