Title :
Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects
Author :
Glaser, U. ; Hubner, U. ; Vierhaus, H.T.
Keywords :
Automatic test pattern generation; Circuit faults; Circuit testing; Computer science; Electrical fault detection; Fault detection; Integrated circuit interconnections; Semiconductor device modeling; Switches; Transistors;
Conference_Titel :
Test Conference, 1992. Proceedings., International
Print_ISBN :
0-7803-0760-7
DOI :
10.1109/TEST.1992.528533
