Title :
Set-valued logic circuits for next generation VLSI architectures
Author :
Aoki, Takafumi ; Higuchi, Tatsuo
Author_Institution :
Dept. of Syst. Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
This paper presents the concept of “set-valued logic” as a foundation for next-generation integrated systems free from interconnection problems. The set-valued logic system employs multiplexable information carriers to achieve highly parallel processing with reduced interconnections. This paper also proposes a new approach to the construction of set-valued logic VLSIs employing pseudo-random sequences as information carriers
Keywords :
VLSI; binary sequences; integrated circuit interconnections; integrated logic circuits; multiplexing; highly parallel processing; information carriers; interconnection problems; multiplexable information carriers; next generation VLSI architectures; next-generation integrated systems; pseudo-random sequences; set-valued logic VLSIs; set-valued logic circuits; set-valued logic system; Logic circuits; Very large scale integration;
Conference_Titel :
Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on
Conference_Location :
Fukuoka
Print_ISBN :
0-8186-8371-6
DOI :
10.1109/ISMVL.1998.679324
