A pixel readout chip with an internal tunable delay and binary output for an LHC vertex detector

The Omega3/LHC1 pixel detector readout chip is aimed at future LHC vertex detector applications. It is the latest member of the Omega series designed at CERN. It comprises an array of 128×16 pixel readout cells of 50 μm×500 μm and the chip contains more than 800,000 transistors. In the design particular emphasis is given to cell-to-cell and chip-to-chip uniformity, and testability, proven key parameters in existing pixel systems. Each cell contains a full readout chain with preamp, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Each cell can be individually addressed for electrical test and masking. Several operation modes allow full testing and data acquisition with different ways to resolve timing ambiguities. The layout of one cell and the corresponding chip photograph are shown below. We present results obtained from electrical tests of a chip without detector as well as from radioactive source measurements using a chip which has been bump-bonded to a 300 μm thick Si detector. A timewalk of <10 ns and a delay precision of <6 ns rms have been measured. The noise is ~100 e^- rms. The lowest threshold setting is close to 3000 e^- and the non-uniformity has been measured to be ~450 e^- rms at a threshold of 5 000 e^- . Source measurements showed good uniformity of response to both β and γ rays