An efficient implementation of CBC mode Rijndeal AES on an FPGA

Author

Naiem, Ghada Farouk ; Elramly, Salwa ; Hasan, Bahaa Eldeen ; Shehata, Kaled

Author_Institution

Ain Shams Univ., Cairo

fYear

2008

fDate

18-20 March 2008

Firstpage

1

Lastpage

8

Abstract

Due to the exponential growth of wireless and mobile applications, security has become a paramount design aspect. In this paper we propose an area optimized design for the Rijndeal advanced encryption standard (AES), in the cipher block chaining (CBC) mode. The design is performed using mentor graphics FPGA Adv.Pro. The implementation is performed on XILINX Vertex2P, XC2VP30-7ff896 and utilizes 13% of its resources. The maximum frequency is 405.227 MHz, the output of encryption/decryption takes 60 clock cycles for processing one block message.

Keywords

cryptography; design; field programmable gate arrays; Rijndeal advanced encryption standard; XC2VP30-7ff896; XILINX Vertex2P; area optimized design; cipher block chaining mode; decryption; mentor graphics FPGA Adv.Pro; mobile applications; security; symmetric key cryptography; wireless applications; Clocks; Communication system control; Cryptography; Design engineering; Field programmable gate arrays; Graphics; National security; Presses; Signal generators; Standards publication; Field programmable gate arrays; Security; Symmetric key cryptography;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 2008. NRSC 2008. National

Conference_Location

Tanta Univ.

Print_ISBN

978-977-5031-95-2

Type

conf

DOI

10.1109/NRSC.2008.4542373

Filename

4542373