Title :
Efficient electronic implementation of modified signed-digit trinary carry free adder
Author :
Hossain, M.M. ; Ahmed, J.U. ; Awwal, A.A.S.
Author_Institution :
Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA
Abstract :
An efficient carry-free addition and borrow-free subtraction of modified signed-digit trinary number scheme is presented which may be used for parallel computing application. A digital 2 bit prototype adder was designed and implemented using electrically programmable logic device (EPLD)
Keywords :
adders; digital arithmetic; logic arrays; parallel processing; EPLD; addition rule; borrow-free subtraction; carry-free addition; digital 2 bit prototype adder; electrically programmable logic device; implementation; modified signed-digit trinary carry free adder; parallel computing; Adders; Application software; Computer applications; Computer science; Design engineering; Digital arithmetic; Logic gates; Programmable logic devices; Prototypes;
Conference_Titel :
Aerospace and Electronics Conference, 1993. NAECON 1993., Proceedings of the IEEE 1993 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-1295-3
DOI :
10.1109/NAECON.1993.290913
